Memory arrays which incorporate bipolar, split-emitter memory cells are well known in the bipolar memory array art. A memory array incorporating the usual read selection approach is shown in an article entitled "High-Speed Split-Emitter I.sup.2 L/MTL Memory Cell" by S. K. Wiedmann, D. D. Tang and R. Beresford in IEEE Journal of Solid State Circuits, Vol. SC-16, No. Oct. 5, 1981, pages 429-434. The article is hereby incorporated by reference to show the state of the art. FIG. 1 of the present application shows a memory cell identical to FIG. 1 of the article which will be discussed hereinbelow in some detail. Also, while the article goes into detail to show the read-write selection approaches used, FIG. 2 of the present application will be discussed hereinbelow specifically in connection with the read selection approach of the prior art. To the extent that additional delays can occur under a worst-case bit patters (when all the unselected cells are storing a different value from the selected cell), the prior art has neither recognized or provided a solution to this problem. The present teaching minimizes cell access time while at the same time, minimizing the drive power required.
U.S. Pat. No. 4,319,344 filed May 30, 1980 and assigned to the same assignee as the present application, shows an MTL memory array in which a selected pair of bit lines is discharged through a selected cell coupled to the selected pair of bit lines while simultaneously the nonselected pairs of bit lines are discharged through a common switch into nonselected word lines. In the present application, prior to the word select, all the nonselected bit lines are precharged to a reference voltage, that is about 600 mV lower than the bit line voltage at standby, during a read cycle while the selected bit line capacitances are not charged at all.
It is, therefore, an object of the present invention to reduce additional delay during a read cycle due to a worst-case bit pattern on the memory cell array while simultaneously minimizing required drive power.
Another object of the present invention is to provide for the precharging of unselected bit lines to that upon actuation of the read current sources to all bit lines, the read currents of the selected cell flow to the selected word line.
Yet another object of the present invention is to prevent dynamic currents of unselected cells from flowing into the booster resisters of the selected cell by charging only the bit line capacitances of unselected cells.
Still another object of the present invention is to provide a cell selection approach which minimizes cell read delay.